When a given DAC is updated to a new digital input code, the output of the DAC changes to try and generate the new analog signal. The internal components of the DAC include a plurality of switches (i.e., field effect transistors). The effects of switching digital circuits within the DAC to change the analog output signal may cause glitches to occur. Glitches may appear at the DAC output as spikes in voltage. Glitches may be caused by two different mechanisms. First, glitches can arise due to capacitive coupling of components within the DAC circuit during transitions of the digital elements. Second, glitches can arise due to asynchronous operation of the components (e.g., some FETS may turn off slower than the FETs turn on due to mismatches in the rise time and fall time of the FETS and/or routing of signals to the FETs). Deglitching techniques have been implemented in some analog circuits to alleviate the effects of glitching. One common technique is to implement a sample and hold circuit coupled to the output of the DAC.
FIG. 1 illustrates a deglitching circuit 100 that implements a sample and hold technique, in accordance with the prior art. The circuit 100 includes an N-bit latch 110, an N-bit DAC 120, a switch 130 (e.g., a Field Effect Transistor or FET), an operational amplifier (Op Amp) 140, and a capacitor 150. The latch 110 receives an N-bit digital input signal and a LD signal. The LD signal is used to latch the N-bit digital input signal to prevent unexpected transitions of the DAC 120. When the LD signal transitions from low to high, a SW signal that controls the switch 130 transitions from high to low, thereby initializing the transition of the DAC output (VDAC). While the LD signal is high, the input to the latch 110 is passed through to the output of the latch 110. The switch 130 isolates the DAC output from the Op Amp 140 when the SW signal is low, thereby preventing any glitches from affecting the analog output signal (VOUT). After a short interval, the LD signal transitions from high to low, latching the N-bit input signal at the input to the DAC 120, but the SW signal remains low. When the switch 130 is open, the capacitor 150 stores the DAC output voltage from the previous sample time such that VOUT remains approximately constant (minus leakage current through the switch 130 and the Op Amp 140) while the DAC 120 transitions to the new output voltage. The DAC output is allowed to settle for a settling time, and then the SW signal transitions from low to high thereby connecting VDAC to the capacitor 150 and the input of the Op Amp 140. The analog output, VOUT, transitions from the old value to the new value and the capacitor 150 drains or stores energy to match the DAC output, VDAC.
However, the conventional sample and hold technique shown in FIG. 1 has some associated issues. First, the switch 130 must be driven by a voltage level much higher than the analog signal in order to ensure proper operation of the switch 130. Second, a charge-injection due to the operation of the switch 130 is still present (i.e., capacitive discharge of the transistor may still cause glitches at the input of the Op Amp 140. Third, the Op Amp 140 may introduce noise at the output of the Op Amp 140. Thus, there is a need for addressing this issue and/or other issues associated with the prior art.